By use of the term "communication discipline", there is meant the set of rules or criteria governing the message format used by a particular remote peripheral device in its data transfer operations via communication lines to a central station with its main host computer. Some of the factors differentiating the various communication disciplines involved are: sychronous operation, synchronization, asynchronous operation, start and end of message sequence, message segment length, and so on.
Since there is no standard communication discipline which is common to all peripheral data communication terminals, it was generally required that a system include individually separate communication controllers to accommodate each different discipline handled by the system. Further, since new types of peripherals with different disciplines are often developed, this would in turn require that a new communications controller be designed on a system to accommodate this type of unit.
It has long been the purpose of those manufacturers and users of data communication networks and subsystems to increase the throughput of data per unit time and per unit amount of equipment; also to simplify and economize in the number of elements involved while providing reliable data communications to and from remote stations in the most efficient manner.
Many data communication subsystems have used controllers, not only to handle the individual idiosyncrasies of the various types of data-comm peripheral terminals, but also have used controllers with insufficient control capabilities such that the main host computer must continually be actively involved with every step of the process involving data transfers to and from the remote terminal devices.
As indicated in the previously referenced patents, one way of reducing the complexity and cost, in addition to getting better controllability of a data communications network, is to relieve the main host processor of most of its monitoring and control functions and to place them in the hands of peripheral-controllers which maintain communication capability with remote terminal devices and which, at selected times, communicate back to the main host system to send data or to receive data from it.
Often problems arise as to just how the architectural and functional structure of a network should be arranged to provide the most efficient use of components for data transfers between remote terminals and a central main host computer or a plurality of such host computers.
The presently described data communication network which permits one or more main host computer systems to operate a large plurality of remote terminal devices for data communication purposes, provides modular circuitry for controlling data transfers whereby up to 16 data communication lines from remote terminals are connected to 16 line adapters which are part of a Line Support Processor which sees to it that the various different line communication disciplines are satisfied and which then provides a common line discipline for operations with a Network Support Processor. The Network Support Processor receives initiating data transfer instructions from either a single main host processor or any one of a plurality of up to four main host processors, and sees to the execution of the required data transfers between remote data terminals and the particular host computer which initiated the data transfer instruction. Communications between the Line Support Processor and the Network Support Processor are standardized and not subject to vagaries of the various disciplines required for the remote data communication terminals. The Network Support Processor and its satellite Line Support Processors constitute front-end controllers which permit distributed processing functions to occur in the architecture of the communication network.
The Network Support Processor used herein is integrally provided with a memory control circuit to modularize its functions on slide-in circuit cards. This memory control circuit of the network support processor basically provides memory accessability to a master processor and slave processor for the use of a shared memory storage means.